BESCHREIBUNG

The LTC4307 hot swappable, 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. The LTC4307 provides bidirectional buffering, keeping the backplane and card capacitances isolated. Low offset and high VOL tolerance allows multiple devices to be cascaded on the clock and data busses. If SDAOUT or SCLOUT are low for 30ms, the LTC4307 will automatically break the bus connection. At this time the LTC4307 automatically generates up to 16 clock pulses on SCLOUT in an attempt to free the bus. A connection will resume if the stuck bus is cleared.

During insertion, the SDA and SCL lines are pre-charged to 1V to minimize bus disturbances. When driven high, the ENABLE input allows the LTC4307 to connect after a stop bit or bus idle. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT. READY is an open-drain output which indicates that the backplane and card sides are connected.

 

FEATURES

Bidirectional Buffer with Stuck Bus Recovery

60mV Buffer Offset Independent of Load

30ms Stuck Bus Timeout

Compatible with Non-Compliant VOL I2C Devices

Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane

±5kV Human Body Model ESD Protection

Isolates Input SDA and SCL Line from Output

Compatible with I2CTM, I2C Fast Mode and SMBus

READY Open-Drain Output

1V Precharge on All SDA and SCL Lines

High Impedance SDA, SCL Pins for VCC = 0V

Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP Packages

 

APPLICATIOS

Live Board Insertion

Servers

Capacitance Buffer/Bus Extender

RAID Systems

ATCA

 

OPERATION

Start-Up

When the LTC4307 first receives power on its VCC pin, either during power-up or live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2V (typ). This is to ensure that the LTC4307 does not try to function until it has enough voltage to do so.

Connection Circuitry

Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. The LTC4307 is tolerant of I2C bus DC logic low voltages up to the 0.3VCC VIL I2C specifi cation. When the LTC4307 senses a rising edge on the bus, it deactivates its pull-down devices for bus voltages as low as 0.48V and activates its accelerators. This methodology maximizes the effectiveness of the rise time accelerator circuitry and maintains compatibility with the other devices in the LTC4300 bus buffer family. Care must be taken to ensure that devices participating in clock stretching or arbitration force logic low voltages below 0.48V at the LTC4307 inputs.

Propagation Delays

During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line. If the pull-up resistors are the same, a difference in rise time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 2 for VCC = 5.5V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective propagation delay is negative.

 

ANWENDUNGSINFORMATIONEN

Live Insertion and Capacitance Buffering Application

The LTC4307 that take advantage of the LTC4307’s Hot SwapTM , capacitance buffering and precharge features. If the I/O cards were plugged directly into the backplane without the LTC4307

buffer, all of the backplane and card capacitances would add directly together, making rise-time and fall-time requirements diffi cult to meet. Placing an LTC4307 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4307 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the LTC4307, which is less than 10pF.