FeaTures

6A Output Current

2.25V to 5.5V Input Voltage Range

Low Output Ripple Burst Mode® Operation: IQ = 75µA

±1% Output Voltage Accuracy

Output Voltage Down to 0.6V

High Efficiency: Up to 95%

Low Dropout Operation: 100% Duty Cycle

Programmable Slew Rate on SW Node Reduces Noise and EMI

Adjustable Switching Frequency: Up to 4MHz

Optional Active Voltage Positioning (AVP) with Internal Compensation

Selectable Pulse-Skipping/Forced Continuous/Burst Mode Operation with Adjustable Burst Clamp

Programmierbarer Soft-Start

Inputs for Start-Up Tracking or External Reference

DDR Memory Mode, IOUT = ±3A

Available in a 24-Pin 3mm × 5mm QFN Thermally Enhanced Package

 

applicaTions

Point-of-Load Supplies

Distributed Power Supplies

Portable Computer Systems

DDR Memory Termination

Handheld Devices

 

DescripTion

The LTC®3616 is a low quiescent current monolithic synchronous buck regulator using a current mode, constant frequency architecture. The no-load DC supply current in sleep mode is only 70µA while maintaining the output voltage (Burst Mode operation) at no load, dropping to zero current in shutdown. The 2.25V to 5.5V input supply voltage range makes the LTC3616 ideally suited for single Li-Ion as well as fixed low voltage input applications. 100% duty cycle capability provides low dropout operation, extending the operating time in battery-powered systems.

The operating frequency is externally programmable up to 4MHz, allowing the use of small surface mount inductors. For switching noise-sensitive applications, the LTC3616 can be synchronized to an external clock at up to 4MHz.

Forced continuous mode operation in the LTC3616 reduces noise and RF interference. Adjustable compensation allows the transient response to be optimized over a wide range of loads and output capacitors.

The internal synchronous switch increases efficiency and eliminates the need for an external catch diode, saving external components and board space. The LTC3616 is offered in a leadless 24-pin 3mm × 5mm thermally enhanced QFN package.

 

operaTion

Main Control Loop

The LTC3616 is a monolithic, constant frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power switch. The peak inductor cur rent at which the current comparator trips is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.6V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. Typical voltage range for the ITH pin is from 0.1V to 1.05V with 0.45V corresponding to zero current.

When the top power switch shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the next clock cycle begins. The bottom current limit is typically set at –8A for forced continuous mode and 0A for Burst Mode operation and pulse-skipping mode.

The operating frequency defaults to 2.25MHz when RT/SYNC is connected to SVIN, or can be set by an external resistor connected between the RT/SYNC pin and ground, or by a clock signal applied to the RT/SYNC pin. The switching frequency can be set from 300kHz to 4MHz.

Overvoltage and undervoltage comparators pull the PGOOD output low if the output voltage varies more than ±7.5% (typical) from the set point.

Burst Mode Operation—Internal Clamp

Connecting the MODE pin to SGND enables Burst Mode operation with an internal clamp. In Burst Mode operation the internal power switches operate intermittently at light loads. This increases efficiency by minimizing switching losses. During the intervals when the switches are idle, the LTC3616 enters sleep state where many of the internal circuits are disabled to save power. During Burst Mode operation, the minimum peak inductor current is internally clamped and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below the internal clamp, the burst comparator trips and enables sleep mode. During sleep mode, the power MOSFETs are held off and the load current is solely supplied by the output capacitor. When the output voltage drops, the top power switch is turned back on and the internal circuits are re-enabled. This process repeats at a rate that is dependent on the load current