MAX3280EAUK+T

Allgemeine Beschreibung

The MAX3280E/MAX3281E/MAX3283E/MAX3284E are single receivers designed for RS-485 and RS-422 communication. These devices guarantee data rates up to 52Mbps, even with a 3V power supply. Excellent propagation delay (15ns max) and package-to-package skew time (8ns max) make these devices ideal for multidrop clock distribution applications.

The MAX3280E/MAX3281E/MAX3283E/MAX3284E have true fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are opened or shorted. The receiver output will be a logic high if all transmitters on a terminated bus are disabled (high impedance). These devices feature 1/4-unit-load receiver input impedance, allowing up to 128 receivers on the same bus.

The MAX3280E is a single receiver available in a 5-pin SOT23 package.

Anwendungen

Clock Distribution

Telecom Racks

Basisstationen

Industrielle Steuerung

Local Area Networks

Automobilindustrie

Vorteile und Merkmale

ESD-Schutz:

±15kV Human Body Model

±6kV IEC 1000-4-2, Contact Discharge

±12kV IEC 1000-4-2, Air-Gap Discharge

Guaranteed 52Mbps Data Rate

Guaranteed 15ns Receiver Propagation Delay

Guaranteed 2ns Receiver Skew

Guaranteed 8ns Package-to-Package Skew Time

VL Pin for Connection to FPGAs/ASICs

Allow Up to 128 Transceivers on the Bus  (1/4-unit-load)

Tiny SOT23 Package

True Fail-Safe Receiver

-7V to +12V Common-Mode Range

3V to 5.5V Power-Supply Range

Enable (High and Low) Pins for Redundant Operation

Three-State Output Stage (MAX3281E/MAX3283E)

Thermal Protection Against Output Short Circuit

AEC-Q100 (MAX3280EAUK/V+ Only)

Detaillierte Beschreibung

The MAX3280E/MAX3281E/MAX3283E/MAX3284E are single, true fail-safe receivers designed to operate at data rates up to 52Mbps. The fail-safe architecture guarantees a high output signal if both input terminals are open or shorted together. See the True Fail-Safe section. This feature assures a stable and predictable output logic state with any transmitter driving the line. These receivers function with a 3.3V or 5V supply voltage and feature excellent propagation delay times (15ns).

The MAX3280E is a single receiver available in a 5-pin SOT23 package. The MAX3281E (EN, active high) and MAX3283E (EN, active low) are single receivers that also contain an enable pin. Both the MAX3281E and MAX3283E are available in a 6-pin SOT23 package. The MAX3284E is a single receiver that contains a VL pin, which allows communication with low-level logic included in digital FPGAs. The MAX3284E is available in a 6-pin SOT23 package.

The MAX3284E’s low-level logic application allows users to set the logic levels. A logic high level of 1.65V will limit the maximum data rate to 20Mbps.

±15kV ESD Protection

ESD-protection structures are incorporated on the receiver input pins to protect against ESD encountered  during handling and assembly. The MAX3280E/MAX3281E/MAX3283E/MAX3284E receiver inputs (A, B) have extra protection against static electricity found in normal operation. Maxim’s engineers developed state-of-the-art structures to protect these pins against ±15kV ESD without damage. After an ESD event, this family of parts continues working without latchup.ESD protection can be tested in several ways. The receiver inputs are characterized for protection to the following:

±15kV using the Human Body Model

±6kV using the Contact Discharge method specified in IEC 1000-4-2 (formerly IEC 801-2)

±12kV using the Air-Gap Discharge method specified in IEC 1000-4-2 (formerly IEC 801-2)

True Fail-Safe

The MAX3280E/MAX3281E/MAX3283E/MAX3284E guarantee a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This guaranteed logic high is achieved by setting the receiver threshold between -50mV and -200mV. If the differential receiver input voltage (VA – VB) is greater than or equal to -50mV, RO is logic high. If (VA – VB) is less than or equal to -200mV, RO is logic low.

In the case of a terminated bus with all transmitters disabled, the receiver’s differential input voltage is pulled to ground by the termination. This results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the ±200mV EIA/TIA-485 standard.