DESCRIPCIÓN GENERAL

The AD96687 is ultrafast voltage comparators.The AD96685 is a single comparator with 2.5 ns propagationdelay; the AD96687 is an equally fast dual comparator. Bothdevices feature 50 ps propagation delay dispersion which is aparticularly important characteristic of high-speed comparators.It is a measure of the difference in propagation delay underdiffering overdrive conditions.A fast, high precision differential input stage permits consistentpropagation delay with a wide variety of signals in the common mode range from –2.5 V to +5 V. Outputs are complementarydigital signals fully compatible with ECL 10 K and 10 KH logicfamilies. The outputs provide sufficient drive current to directlydrive transmission lines terminated in 50 Ω to –2 V. A levelsensitive latch input which permits tracking, track-hold, orsample-hold modes of operation is included.The AD96687 is available in industrial range –25°C to +85°C,in 16-pin DIP, SOIC, and 20-lead PLCC.

 

CARACTERÍSTICAS

Fast: 2.5 ns Propagation Delay

Low Power: 118 mW per Comparator

Packages: DIP, SOIC, PLCC

Power Supplies: +5 V, –5.2 V

Logic Compatibility: ECL

50 ps Delay Dispersion

 

APLICACIONES

High Speed Triggers

High Speed Line Receivers

Threshold Detectors

Window Comparators

Peak Detectors

 

INFORMACIÓN SOBRE APLICACIONES

The AD96687 comparators are very high speed devices.Consequently, high speed design techniques must be employedto achieve the best performance. The most critical aspect of anyAD96687 design is the use of a low impedanceground plane.Another area of particular importance is power supply decoupling.Normally, both power supply connections should be separately decoupled to ground through 0.1 µF ceramic and 0.001 µF mica capacitors. The basic design of comparator circuits makes the negative supply somewhat more sensitive to variations. As a result, more attention should be placed on ensuring a “clean” negative supply. The LATCH ENABLE input is active LOW (latched). If the latching function is not used, the LATCH ENABLE input should be grounded (ground is an ECL logic HIGH). The LATCH ENABLE input of the AD96687 should be tied to –2.0 V or left “floating,” to disable the latching function. An alternate use of the LATCH ENABLE input is as a hysteresis control input. Occasionally, one of the two comparator stages within the AD96687 will not be used. The inputs of the unused comparator should not be allowed to “float.” The high internal gain may cause the output to oscillate (possibly affecting the other comparator which is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also grounding the LATCH ENABLE input. The best performance will be achieved with the use of proper ECL terminations. The open-emitter outputs of the AD96685/ AD96687 are designed to be terminated through 50 Ω resistors to –2.0 V, or any other equivalent ECL termination. If high speed ECL signals must be routed more than a few centimeters, MicroStrip or StripLine techniques may be required to ensure proper transition times and prevent output ringing.AD96687 have been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay dispersion is the change in propagation delay which results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the AD96685/AD96687 are far less sensitive to input variations than most comparator designs.

 

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD96687 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.