DESCRIPTION GÉNÉRALE

The ADATE207 is a timing generator and formatter for automatic test equipment (ATE) equipment. The ADATE207 provides four independent channels with a 100 MHz base vector rate of timing and formatting for ATE digital pins. It interfaces between the pattern memory,and the driver, comparator, and load (DCL) chips for complete digital pins. The ADATE207 accepts up to eight bits of pattern data per pin and can produce formatted outputs and perform comparisons of DUT expected responses.

Each channel of the ADATE207 provides 256 selectable waveforms, wherein each waveform consists of up to four possible events. Each event consists of a programmable timing edge and a STIL-compatible (IEEE Standard 1450-1999) set.

Each timing edge generator can produce an edge with a span of four periods with a 39.06 ps edge placement resolution. The delay  generators use a reference master clock of 100 MHz and provide programmable delays based upon counts of the clock and a compensated CMOS analog timing vernier. The programmable delay generators can be additionally delayed by a global 8-bit input value that is shared across all edges.

The format and compare logic support ×2 pin multiplexing to allow the trading of pin count for speed.

Each channel provides a 4-bit DUT output capture supporting mixed signal receive memory applications. The fail detection logic includes a 32-bit fail accumulation register per channel.

An external TMU is supported with three 8-to-1 multiplexers. This allows the dual comparator outputs of any pin to be multiplexed to any of the three outputs: arm, start, or stop signals.

 

CARACTÉRISTIQUES

4-channel timing formatter

256 waveforms per channel

4 independent event edges per waveform

STIL IEEE 1450-1999-compatible events

4-period range for each edge

39.06 ps timing resolution

2.5 ns minimum edge refire rate

All drive formats supported

100 MHz base vector rate ×2 and ×4 high speed modes ×2 pin multiplexing

1 ns minimum pulse width 32-bit fail counter per channel

4-bit pin capture per channel

Air cooled, low power CMOS design

6 W at 100 MHz base rate

2.5 V power supply

Differential DCL interface control

TMU multiplexer

 

CANDIDATURES

Automatic test equipment (ATE) High speed digital instrumentation Pulse generation

 

THÉORIE DU FONCTIONNEMENT

WAVEFORM MEMORY

Pattern data is used to address the waveform memory and is eight bits wide per channel, supporting 256 unique waveforms. The data width of the waveform memory is 26 bits wide per event or 104 bits wide per pin. The waveform memory data bits are partitioned into two fields, a 22-bit wide delay field, and a 4-bit event code field. The waveform memory is dual port allowing CPU access during pattern bursting. Pattern data is used as a pointer to one of the defined 256 waveforms, and can be partitioned into vector data and a time set pointer. Using three bits of vector data for the pin state, the other five bits can be used as 32 possible time sets. Supporting dual I/O per cycle, two sets of 3-bit vector data can be used in combination with two bits of a time set pointer providing four

possible time sets. A straightforward trade off in time sets vs. device vectors per tester cycle is possible.  Pattern data is qualified with the input signal PAT_DATA_VALID. When asserted, the pattern data is evaluated. When not asserted, events and timing edges are disabled and the input pattern data is ignored.

EVENT GENERATORS

Each channel has four programmable event generators. Each event generator inputs a delay, an event code from the waveform memory, and an 8-bit INPUT_DELAY. The waveform delay and the 8-bit INPUT_DELAY combine to produce programmable delays from T0 cycle starts. Each programmable delay can span up to 4 T0 periods and up to 163 μs with a nominal delay resolution of 39.06 ps. There are 16 possible events. These events are

compatible with STIL waveform events, as shown in Table 8, to create all of the conventional drive and compare formats. There is a programmable pipeline delay with 2.5 ns resolution between the drive events and the compare events allowing for round trip delay (RTD) compensation.