DESCRIPTION GÉNÉRALE

The ADA4807-1 (single), ADA4807-2 (dual), and ADA4807-4 (quad) are low noise, rail-to-rail input and output, voltage feedback amplifiers. These amplifiers combine low power, low noise, high speed, and dc precision to provide an attractive solution for a wide range of applications from high resolution data acquisition instrumentation to high performance battery powered and high component density systems where power consumption is of key importance.&nbsp

With only 1.0 mA of supply current per amplifier, the ADA4807-1/ ADA4807-2/ADA4807-4 feature the lowest input voltage noise among high speed, rail-to-rail input/output amplifiers in the industry and offer a wide bandwidth, high slew rate, fast settling time, and excellent distortion performance. Additionally, these amplifiers offer very low input offset voltage and drift performance, making them ideal for driving multiplexed and high throughput precision 16-/18-bit successive approximation registers (SARs) and 24-bit-&nbspADCs.

These amplifiers are fully specified at +3 V, +5 V, and ±5 V supplies and can operate over the industrial −40°C to +125°C temperature range.

The ADA4807-1 is available in 6-lead SOT-23 and space-saving 6-lead SC70 packages. The ADA4807-2 is available in an 8-lead MSOP and a compact, 3 mm × 3 mm, 10-lead LFCSP. The ADA4807-4 is available in a 14-lead TSSOP package.

 

THÉORIE DU FONCTIONNEMENT

The ADA4807-1/ADA4807-2/ADA4807-4 have a rail-to-rail input stage with an input range that goes 200 mV beyond either rail. A PNP transistor input pair is active for a majority of the input range, while an NPN transistor input pair is active for the common-mode voltages within 1.3 V of the positive rail. The ADA4807-1/ADA4807-2/ADA4807-4 are fabricated using the Analog Devices, Inc., third generation, extra fast complementary bipolar (XFCB) process resulting in exceptionally good distortion, noise, slew rate, and settling characteristics for 1 mA devices. Given traditional rail-to-rail input architecture performance, the input 1/f noise is surprisingly low, and the current noise is only 0.7 pA/√Hz for a 3 nV/√Hz voltage noise. Typical high slew rate devices suffer from increased current noise because of input pair degeneration and higher input stage current. The ADA4807-1/ ADA4807-2/ADA4807-4 exceed current benchmark parameters given the performance of the XFCB process.

The multistage design of the ADA4807-1/ADA4807-2/ ADA4807-4 has excellent precision specifications, such as input drift, offset, open-loop gain, CMRR, and PSRR. Typical harmonic distortion numbers fall in the range of −130 dBc for a 10 kHz fundamental (see the Distortion and Noise section). This level of performance makes the ADA4807-1/ADA4807-2/ADA4807-4 the best choices when driving 18-bit precision converters.

The ADA4807-1/ADA4807-2 are optimized for a low shutdown current (4 μA maximum), in the order of a few microamperes. In power sensitive applications, this can eliminate the use of a power FET and enable time interleaved power saving operation schemes.&nbsp

The rail-to-rail input stage is useful in many different applications. Although the precision is reduced from input to input, many applications can tolerate this loss when the alternative is no functionality at all. The positive rail input range is indispensable for servo loops with a high-side input range.

The ADA4807-1/ADA4807-2/ADA4807-4 input operates 200 mV beyond either rail. Internal protection circuitry prevents the output from phase inverting when the input range is exceeded. When the input exceeds a diode beyond either rail, internal electrostatic discharge (ESD) protection diodes source or sink current through the input.

 

ADC DRIVING WITH DYNAMIC POWER SCALING

In power sensitive applications, the ADA4807-1/ADA4807-2 can be switched on prior to the ADC turning on. Figure 78 shows the timing diagram for dynamically power scaling the ADA4807-1/ADA4807-2 with the AD7982 configuration shown in Figure 79. The falling edge of the DISABLE signal must align with the rising edge of the CONV signal of the ADC to obtain a clean data acquisition. Figure 79 gives the FFT for driving a fully differential signal chain with a 1.2 µs on time as shown in Figure 78. With this method, the ADA4807-1/ADA4807-2 quiescent current (per amplifier) is reduced from 2 mA to 0.25 mA. Figure 81 gives the FFT for dynamically power scaling a single-ended input signal chain into a differential ADC with a 4 µs on time as shown in Figure 80. This configuration results in a quiescent current reduction of 20%.