Description :

 The CY7C1444KV33/CY7C1445KV33 SRAMs integrate 1M × 36/2M × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock (CLK) input. The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. This part supports byte write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1444KV33/CY7C1445KV33 SRAMs operate from a +3.3 V core power supply while all outputs operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

 

Features:

■ Supports bus operation up to 250 MHz

■ Available speed grades is 250 MHz

■ Registered inputs and outputs for pipelined operation

■ Optimal for performance (double-cycle deselect)

■ Depth expansion without wait state

■ 3.3-V core power supply

■ 2.5-V or 3.3-V I/O power supply

■ Fast clock-to-output times

❐ 2.5 ns (for 250-MHz device)

■ Provide high-performance 3-1-1-1 access rate

■ User-selectable burst counter supporting interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

■ Asynchronous output enable

■ CY7C1444KV33, CY7C1445KV33 available in JEDEC-standard Pb-free 100-pin TQFP packages

■ “ZZ” sleep mode option

 

Aperçu fonctionnel

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1444KV33/CY7C1445KV33 support secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous chip selects CE1, CE2, CE3 and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH.

Exceeding maximum ratings may shorten the useful life of the device.

 

Document History Page

04/09/2015 Changed status from Preliminary to Final.

05/07/2015 Updated Functional Overview: Updated ZZ Mode Electrical Characteristics: Changed maximum value of IDDZZ parameter from 89 mA to 75 mA

07/05/2016 Updated Neutron Soft Error Immunity: Updated values in “Typ” and “Max” columns corresponding to LSBU parameter. Updated to new template.