Description

PIC12(L)F1571/2 microcontrollers combine the capabilities of 16-bit PWMs with Analog to suit a variety of applications. These devices deliver three 16-bit PWMs with independent timers for applications where high resolution is needed, such as LED lighting, stepper motors, power supplies and other general purpose applications. The core independent peripherals (16-bit PWMs, Complementary Waveform Generator), Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART) and Analog (ADCs, Comparator and DAC) enable closed-loop feedback and communication for use in multiple market segments. The EUSART peripheral enables the communication for applications such as LIN.

This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

  • Automatic Interrupt Context Saving
  • 16-Level Stack with Overflow and Underflow
  • File Select Registers
  • Instruction Set

 

Caractéristiques

C Compiler Optimized RISC Architecture

Only 49 Instructions

Operating Speed:

– DC – 32 MHz clock input

– 125 ns minimum instruction cycle

Interrupt Capability

16-Level Deep Hardware Stack

Two 8-Bit Timers

One 16-Bit Timer

Three Additional 16-Bit Timers available using the 16-Bit PWMs

Power-on Reset (POR)

Power-up Timer (PWRT)

Low-Power Brown-out Reset (LPBOR)

Programmable Watchdog Timer (WDT) up to 256s

Programmable Code Protection

 

eXtreme Low-Power (XLP) Features:

Sleep mode: 20 nA @ 1.8V, Typical

Watchdog Timer: 260 nA @ 1.8V, Typical

Courant de fonctionnement :

– 30 A/MHz @ 1.8V, typical

 

Digital Peripherals:

16-Bit PWM:

– Three 16-bit PWMs with independent timers

– Multiple Output modes (Edge-Aligned, Center-Aligned, Set and Toggle on Register Match)

– User settings for phase, duty cycle, period, offset and polarity

– 16-bit timer capability

– Interrupts generated based on timer matches with Offset, Duty Cycle, Period and Phase registers

Complementary Waveform Generator (CWG):

– Rising and falling edge dead-band control

– Multiple signal sources

Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART):

– Supports LIN applications

 

ENHANCED MID-RANGE CPU

This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

  • Automatic Interrupt Context Saving
  • 16-Level Stack with Overflow and Underflow
  • File Select Registers
  • Instruction Set

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code.

These devices have a hardware stack memory, 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a Software Reset.

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs.

There are 49 instructions for the enhanced midrange CPU to support the features of the CPU.

 

MEMORY ORGANIZATION

These devices contain the following types of memory:

  • Program Memory:

– Configuration Words

– Device ID

– User ID

– Flash Program Memory

  • Data Memory:

– Core Registers

– Special Function Registers

– General Purpose RAM

– Common RAM

The following features are associated with access and control of program memory and data memory:

  • PCL and PCLATH
  • Stack
  • Indirect Addressing