概要

The DS1856 dual, temperature-controlled, nonvolatile (NV) variable resistors with three monitors consists of two 256-position, linear, variable resistors; three analog monitor inputs (MON1, MON2, MON3); and a direct-to-digital temperature sensor. The device provides an ideal method for setting and temperature-compensating bias voltages and currents in control applications using minimal circuitry. The variable resistor settings are stored in EEPROM memory and can be accessed over the 2-wire serial bus.

Relative to other members of the family, the DS1856 is essentially a DS1859 with a DS1852-friendly memory map. In particular, the DS1856 can be configured so the 128 bytes of internal Auxiliary EEPROM memory is mapped into Main Device Table 00h and Table 01h, maintaining compatibility between both the DS1858/DS1859 and the DS1852. The DS1856 also features password protection equivalent to the DS1852, further enhancing compatibility between the two.

 

アプリケーション

Optical Transceivers

Optical Transponders

Instrumentation and Industrial Controls

RF Power Amps

Diagnostic Monitoring

 

特徴

SFF-8472 Compatible

Five Monitored Channels (Temperature, VCC, MON1, MON2, MON3)

Three External Analog Inputs (MON1, MON2, MON3) That Support Internal and External Calibration

Scalable Dynamic Range for External Analog Inputs

Internal Direct-to-Digital Temperature Sensor

Alarm and Warning Flags for All Monitored Channels

Two Linear, 256-Position, Nonvolatile Temperature-Controlled Variable Resistors

Resistor Settings Changeable Every 2°C

Three Levels of Security

Access to Monitoring and ID Information Configurable with Separate Device Addresses

2-Wire Serial Interface

Two Buffers with TTL/CMOS-Compatible Inputs and Open-Drain Outputs

Operates from a 3.3V or 5V Supply

-40°C to +95°C Operating Temperature Range

 

詳細

The user can read the registers that monitor the VCC, MON1, MON2, MON3, and temperature analog signals. After each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. The signals also have alarm and warning flags that notify the user when the signals go above or below the user-defined value. Interrupts can also be set for each signal.

The position values of each resistor can be independently programmed. The user can assign a unique value to each resistor for every 2°C increment over the-40°C to +102°C range.

Two buffers are provided to convert logic-level inputs into open-drain outputs. Typically, these buffers are used to implement transmit (Tx) fault and loss-of-signal (LOS) functionality. Additionally, OUT1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits.

 

Memory Description

The memory of the DS1856 is divided into two areas referred to as the Main Device and the Auxiliary Device. The Main Device comprises all of the DS1856 specific memory while the Auxiliary Device consists of 128 bytes of general-purpose EEPROM and is especially useful in GBIC applications. Main and Auxiliary memories can be accessed by two separate 2-wire slave addresses. The Main Device address is A2h (byte 8Ch, when ADFIX = 1) and the Auxiliary Device address is A0h (fixed). A configuration bit, ADEN, determines whether the DS1856 uses one or two 2-wire slave addresses. This feature can be used to save component count in SFF applications or other applications where both GBIC and monitoring functions are implemented and two device addresses are needed.

All of the DS1856’s memory including the Auxiliary memory is accessed using only the Main Device address. The Auxiliary Device memory is mapped into Table 00 and Table 01 in the Main Device. Both tables map to the same block of physical memory. This is done to improve the compatibility between previous members of this IC family such as the DS1858/DS1859 and the DS1852. In this configuration, the DS1856 ignores communication using the Auxiliary Device address.

The DS1856 2-wire interface uses 8-bit addressing, which allows up to 256 bytes to be addressed traditionally on a given 2-wire slave address. However, since the Main Device contains more than 256 bytes, a table scheme is used. The lower 128 bytes of the Main Device, memory locations 00h to 7Fh, function as expected and are independent of the currently selected table. Byte 7Fh is the Table Select byte. This byte determines which memory table will be accessed by the 2-wire interface when address locations 80h to FFh are accessed. Memory locations 80h to FFh are accessible only through the Main Device address. The Auxiliary Device address has no access to the tables, but the Auxiliary Device memory can be mapped into the Main Device’s memory space. Valid values for the Table Select byte are shown in the table below.