説明

The STM8S003F3/K3 value line 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. They are referred to as low-density devices in the STM8S microcontroller family reference manual .

The STM8S003F3/K3 value line devices provide the following benefits: performance, robustness and reduced system cost.

Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art technology at 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog, and brown-out reset.Full documentation is offered as well as a wide choice of development tools.

 

Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

  • Harvard architecture
  • 3-stage pipeline
  • 32-bit wide program memory bus – single cycle fetching for most instructions
  • X and Y 16-bit index registers – enabling indexed addressing modes with or without offset and read-modify-write type data manipulations
  • 8-bit accumulator
  • 24-bit program counter – 16-Mbyte linear memory space
  • 16-bit stack pointer – access to a 64 K-level stack
  • 8-bit condition code register – 7 condition flags for the result of the last instruction

Addressing

  • 20 addressing modes
  • Indexed indirect addressing mode for look-up tables located anywhere in the address space
  • Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

  • 80 instructions with 2-byte average instruction size
  • Standard data movement and logic/arithmetic functions
  • 8-bit by 8-bit multiplication
  • 16-bit by 8-bit and 16-bit by 16-bit division
  • Bit manipulation
  • Data transfer between stack and accumulator (push/pop) with direct stack access
  • Data transfer using the X and Y registers or direct memory-to-memory transfers

 

Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

  • R/W to RAM and peripheral registers in real-time
  • R/W access to all resources by stalling the CPU
  • Breakpoints on all program-memory instructions (software breakpoints)
  • Two advanced breakpoints, 23 predefined configurations

 

Interrupt controller

  • Nested interrupts with three software priority levels
  • 32 interrupt vectors with hardware priority
  • Up to 27 external interrupts on six vectors including TLI
  • Trap and reset interrupts

 

Flash program memory and data EEPROM

  • 8 Kbyte of Flash program single voltage Flash memory
  • 128 byte true data EEPROM
  • User option byte area

 

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code).