GENERAL DESCRIPTION

The ADP150 is an ultralow noise (9 µV), low dropout, linear regulator that operates from 2.2 V to 5.5 V and provides up to 150 mA of output current. The low 105 mV dropout voltage at 150 mA load improves efficiency and allows operation over a wide input voltage range.

Using an innovative circuit topology, the ADP150 achieves ultralow noise performance without the necessity of an additional noise bypass capacitor, making it ideal for noise sensitive analog and RF applications. The ADP150 also achieves ultralow noise performance without compromising PSRR or line and load transient performance. The ADP150 offers the best combination of ultralow noise and quiescent current consumption to maximize battery life inportable applications.

The ADP150 is specifically designed for stable operation with tiny 1 µF ± 30% ceramic input and output capacitors to meet therequirements of high performance, space-constrained applications.

The ADP150 is available in 14 fixed output voltage options, rangingfrom 1.8 V to 3.3 V.

Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP150 is available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch WLCSP packages for the smallest footprint solution to meet a variety of portable power applications.

 

THEORY OF OPERATION

The ADP150 is an ultralow noise, low quiescent current, low dropout linear regulator that operates from 2.2 V to 5.5 V and can provide up to 150 mA of output current. Drawing a low 220 µA of quiescent current (typical) at full load makes the ADP150 ideal for battery-operated portable equipment. Shutdown current consumption is typically 200 nA.

Using a proprietary architecture, the ADP150 provides superior noise performance for noise sensitive analog and RF applications without the need for a noise bypass capacitor. The ADP150 is also optimized for use with small 1 µF ceramic capacitors.

Internally, the ADP150 consists of a reference, an error amplifier,a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device that is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage.

The ADP150 is available in 14 output voltage options, ranging from 1.8 V to 3.3 V. The ADP150 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high,VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN.

 

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the ADP150,as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics.

Figure 29 depicts the capacitance vs. the voltage bias characteristic of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.