Description:

The CY7C1471V33 is 3.3 V, 2M × 36 synchronous, flow-through burst SRAM designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33 is equipped with advanced

No Bus Latency (NoBL) logic is required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock qualifies the clock input enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. The maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by two or four-byte write select (BWX) and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

 

Features:

No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
Supports up to 133 MHz bus operations with zero wait states.
Data is transferred on every clock.
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need to use OE
Registered inputs for flow-through operation
Byte Write capability
3.3 V/2.5 V I/O supply (VDDQ)
Fast clock-to-output times
6.5 ns (for 133-MHz device)
Clock enable (CEN) pin to enable clock and suspend operation.
Synchronous self-timed writes
Asynchronous output enable (OE)
CY7C1471V33 is available in JEDEC-standard Pb-free 100-pin TQFP.
Three chip enables (CE1, CE2, CE3) for simple depth expansion
Automatic power-down feature available using ZZ mode or CE deselect
Burst capability—linear or interleaved burst order
Low standby power

 

Functional Overview

The CY7C1471V33 is a synchronous, flow-through burst SRAM designed to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized, and all internal states are maintained. All synchronous operations are qualified with CEN. The maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the write enable (WE). Byte write select (BWX) can be used to conduct byte write operations. Write operations are qualified by the write enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chips enable (CE1, CE2, CE3) and an asynchronous output enable (OE) to simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation.

Single Read Accesses

A read access is initiated when these conditions are satisfied at clock rise: ■ CEN is asserted LOW ■ CE1, CE2, and CE3 are all asserted active. ■ WE are de-asserted HIGH. ■ ADV/LD is asserted as LOW. The address presented to the address inputs is latched into the address register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. On the subsequent clock, another operation (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, output is tri-stated immediately.

Burst Read Accesses

The CY7C1471V33 has an on-chip burst counter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Accesses section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode; a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence and wrap around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. We are latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, and (3) WE is asserted LOW. The address presented to the address bus is loaded into the address register. The Write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise, the data presented to DQs and DQPX (or a subset for Byte Write operations; see Truth Table for Read/Write on page 9 for details) inputs is latched into the device, and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle. The data written during the write operation is controlled by BWX signals. The CY7C1471V33 provides byte write capability that is described in the truth table for read/write on page 9. The input WE with the selected BWX input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1471V33 are common I/O devices, data must not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1471V33 has an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Accesses section. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3), WE inputs are ignored, and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid, nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3 must remain inactive for the duration of tZZREC after the ZZ input returns LOW.