DESCRIPTION

The LTC®1257 is a complete single supply, 12-bit voltage output D/A converter (DAC) in an SO-8 package. The LTC1257 includes an output buffer amplifier, 2.048V volt age reference and an easy to use 3-wire cascadable serial interface. An external reference can be used to override the internal reference and extend the output voltage range to 12V. The power supply current is a low 350µA when operating from a 5V supply, making the LTC1257 ideal for battery-powered applications. The space-saving 8-pin SO package and operation with no external components provide the smallest 12-bit D/A system available.

FEATURES

8-Pin SO Package

Buffered Voltage Output

Built-In 2.048V Reference

500µV/LSB with 2.048V Full Scale

1/2LSB Max DNL Error

Guaranteed 12-Bit Monotonic

3-Wire Cascadable Serial Interface

Wide Single Supply Range: VCC = 4.75V to 15.75V

Low Power: ICC Typ = 350µA with 5V Supply

 

APPLICATIONS

Digital Offset/Gain Adjustment

Industrial Process Control

Automatic Test Equipment

 

PIN FUNCTIONS

CLK (Pin 1): The TTL level input for the serial interface clock.

DIN (Pin 2): The TTL level input for the serial interface data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock.

LOAD (Pin 3): The TTL level input for the serial interface load control. Data is loaded from the shift register into the DAC register, thus updating the DAC output when LOAD is pulled low. The DAC register is transparent as long as LOAD is held low.

DOUT(Pin 4): The output of the shift register which becomes valid on the rising edge of the serial clock. The DOUT pin is driven from GND to VCC by an internal CMOS inverter. Multiple LTC1257s may be cascaded by connecting the DOUT pin to the DIN pin of the next chip.

GND (Pin 5): Ground.

REF (Pin 6): The output of the 2.048V reference and the input to the DAC resistor ladder. An external reference with voltage from 2.475V to VCC – 2.7V may be used to override the internal reference.

 

OPERATION

Serial

Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first and the LSB last. The DAC register loads the data from the shift register when LOAD is pulled low, and remains transparent until LOAD is pulled high and the data is latched.

An internal 5V regulator provides the supply for the digital logic. By limiting the internal digital signal swings to 5V, digital noise is reduced. The buffered output of the 12-bit shift register is available on the DOUT pin which will swing from GND to VCC.

Multiple LTC1257s may be daisy chained together by connecting the DOUT pin to the DIN pin of the next chip, while the clock and load signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the LOAD signal is pulled low to update all of them simultaneously. The maximum clocking rate is 1.4MHz.

Reference

The LTC1257 includes an internal 2.048V reference, mak ing 1LSB equal to 500µV. The internal reference output is turned off when the pin is forced above the reference voltage, allowing an external reference to be connected to the reference pin. The external reference must be greater than 2.475V and less than VCC – 2.7V, and be capable of driving the 10k minimum DAC resistor ladder.

If the reference output is driving a large capacitive load, a series resistor must be added to insure stability. For any capacitive load greater than 1µF, a 10Ω series resistor will suffice.

Voltage Output

The LTC1257 voltage output is able to pull within 2.7V of VCC while sourcing 2mA. A internal NMOS transistor with a 200Ω equivalent impedance pulls the output to ground. The output is protected against short circuits and is able to drive up to a 500pF capacitive load without oscillation. If digital noise on the output causes a problem, a simple 100Ω, 0.1µF RC circuit can be used to filter the noise.