DESCRIPTION

The LTM9011-14 are 8-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73.1dB SNR and 88dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flow-through pinout reduces overall board space requirements.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.
The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode).
The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

 

FEATURES

8-Channel Simultaneous Sampling ADC
73.1dB SNR
88dB SFDR
Low Power: 140mW/113mW/94mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Internal Bypass Capacitance, No External Components
140-Pin (11.25mm × 9mm) BGA Package

 

APPLICATIONS

Communications

Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing

APPLICATIONS INFORMATION

CONVERTER OPERATION
The LTM9011-14 are low power, 8-channel, 14-bit,125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time  (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port.
INPUT DRIVE CIRCUITS

Input Filtering

If possible, there should be an RC low pass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry.

Reference

The LTM9011-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE.
The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 VSENSE. The reference is shared by all eight ADC channels, so it is not possible to independently adjust the input range of individual channels.

Encode Input

The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode, and the single-ended encode mode . The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs. The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times.The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times.