ОБЩЕЕ ОПИСАНИЕ

The ADBMS18181 is a multicell battery stack monitor that measures up to 18 series connected battery cells with a total measurement error (TME) of less than 3.0 mV. The cell measurement range of 0 V to 5 V makes the ADBMS1818 suitable for most battery chemistries. All 18 cells can be measured in 290 µs, and lower data acquisition rates can be selected for high noise reduction.

Multiple ADBMS1818 devices can be connected in series, permitting simultaneous cell monitoring of long, high voltage battery strings. Each ADBMS1818 has an isoSPI™ interface for high speed, RF immune, long distance communications. Multiple devices are connected in a daisy chain with one host processor connection for all devices. This daisy chain can be operated bidirectionally,ensuring communication integrity, even in the event of a fault along the communication path.

The ADBMS1818 can be powered directly from the battery stack or from an isolated supply. The ADBMS1818 includes passive balancing for each cell, with individual pulse-width modulation (PWM) duty cycle control for each cell. Other features include an on-board 5 V regulator, nine general-purpose I/O lines, and a sleep mode, where current consumption is reduced to 6 µA.

 

Standby State

The reference and the ADCs are off. The watchdog timer and/or the discharge timer is running. The DRIVE pin powers the VREG pin to 5 V through an external transistor. Alternatively, VREG can be powered by an external supply.

When a valid ADC command is received or the REFON bit is set to 1 in Configuration Register Group A, the IC pauses for tREFUP to allow the reference to power up and then enters either the REFUP or measure state. Otherwise, if no valid commands are received for tSLEEP (when both the watchdog and discharge timer expire), theADBMS1818 returns to the sleep state. If the discharge timer is disabled, only the watchdog timer is relevant.

 

Measure State

The ADBMS1818 performs ADC conversions in the measure state. The reference and ADCs are powered up.After ADC conversions complete, the ADBMS1818 transitions to either the REFUP or standby state, depending on the REFON bit.

Additional ADC conversions can be initiated more quickly by setting REFON = 1 to take advantage of the REFUP state.Note that non ADC commands do not cause a core state transition.

Only an ADC conversion or diagnostic commands place the core in the measure state.

 

ADC Modes

The ADCOPT bit (CFGAR0, Bit 0) in Configuration Register Group A and the mode selection bits, MD, Bits[1:0], in the conversion command together provide eight modes of operation for the ADC

which correspond to different oversampling ratios (OSRs). In each mode, the ADC first measures the inputs and then performs a calibration of each channel. The names of the modes are based on the –3 dB bandwidth of the ADC measurement.

Mode 7 kHz (normal): In this mode, the ADC has high resolution and low TME. This mode is considered the normal operating mode because of the optimum combination of speed and accuracy.

Mode 27 kHz (fast): In this mode, the ADC has maximum throughput but has some increase in TME. Therefore, this mode is also referred to as the fast mode. The increase in speed comes from a reduction in the OSR. This increase results in an increase in noise and average measurement error. Mode 26 Hz (filtered): In this mode, the ADC digital filter –3 dB frequency is lowered to 26 Hz by increasing the OSR. This mode is also referred to as the filtered mode due to its low –3 dB frequency.

The accuracy is similar to the 7 kHz (normal) mode with lower noise.Modes 14 kHz, 3 kHz, 2 kHz, 1 kHz, and 422 Hz: Modes 14 kHz, 3kHz, 2 kHz, 1 kHz, and 422 Hz provide additional options to set the ADC digital filter –3 dB at 13.5 kHz, 3.4 kHz, 1.7 kHz, 845 Hz, and 422 Hz, respectively. The accuracy of the 14 kHz mode is similar to the 27 kHz (fast) mode. The accuracy of the 3 kHz, 2 kHz, 1 kHz, and 422 Hz modes is similar to the 7 kHz (normal) mode.

The filter bandwidths and the conversion times for these modes are provided . If the core is in the standby state, an additional tREFUP time is required to power up the reference before beginning the ADC conversions. The reference can remain powered up between ADC conversions if the REFON bit in Configuration Register Group A is set to 1 so that the core is in REFUP state after delay tREFUP. The subsequent ADC commands do not have the tREFUP delay before beginning ADC conversions.