ОБЩЕЕ ОПИСАНИЕ

The ADRF6780 is a silicon germanium (SiGe) design, wideband, microwave upconverter optimized for point to point microwave radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.

The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 Ω differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary.

The ADRF6780 upconverter comes in a compact, thermally enhanced, 5 mm × 5 mm LFCSP package. The ADRF6780 operates over the −40°C to +85°C temperature range.

 

ОСОБЕННОСТИ

Wideband RF output frequency range: 5.9 GHz to 23.6 GHz

Two upconversion modes

Direct conversion from baseband I/Q to RF

Single sideband upconversion from real IF

LO input frequency range: 5.4 GHz to 14 GHz

LO doubler for up to 28 GHz

Matched 100 Ω balanced RF output, LO input, and IF input

High impedance baseband inputs

Sideband suppression and carrier feedthrough optimization

Variable attenuator and power detector for Tx power control

Programmable via 4-wire SPI interface

32-lead, 5 mm × 5 mm LFCSP microwave packaging

 

ПРИЛОЖЕНИЯ

Point to point microwave radios

Radar, electronic warfare systems

Instrumentation, automatic test equipment (ATE)

 

ТЕОРИЯ ЭКСПЛУАТАЦИИ

The ADRF6780 is a wideband microwave upconverter optimized for point to point microwave radio designs operating in the 5.9 GHz to 23.6 GHz frequency range. The ADRF6780 is programmed via an SPI.

 

LO INPUT PATH

The LO input path operates from 5.4 GHz to 14 GHz with a LO amplitude range of −6 dBm to +6 dBm. It is built from two modes: ×1 mode (Register 0x03, Bit 2), which provides an LO output frequency equal to the LO input frequency, and ×2 mode (Register 0x03, Bit 3), which doubles the LO output frequency from the LO input frequency. Note that, when enabling the LO ×2 mode (Register 0x03, Bit 3), the LO ×1 mode (Register 0x03, Bit 2) must be disabled.

The LO path is designed to operate differentially. LOIP and LOIN are the inputs to the LO path. It is recommended to use the ADRF6780 with a LO differential input to achieve the best performance.

 

SERIAL PORT INTERFACE (SPI)

The SPI of the ADRF6780 allows the user to configure the device for specific functions or operations via a 4-pin SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDIN, SDTO, and SEN.

The ADRF6780 protocol consists of a write/read bit followed by six register address bits, 16 data bits, and a parity bit. Both the address and data fields are organized MSB first and end with the least significant bit (LSB). For a write, set the first bit to 0, and for a read, set this bit to 1.

The write cycle sampling must be done on the rising edge. The 16 bits of the serial write data are shifted in, MSB to LSB. The ADRF6780 input logic level for the write cycle supports an 1.8 V interface.

For a read cycle, up to 16 bits of serial read data are shifted out, MSB first. After the 16 bits of data shift out, the parity bit shifts out. The output logic level for a read cycle is 1.8 V.

The parity bit always follows the direction of the data. If parity is not used, the transmitting end transmits zero instead of parity. The parity is odd, which means that the total number of ones transmitted during a command, including the read/write bit, the address bit, the data bit, and the parity bit, must be odd.