ОБЩЕЕ ОПИСАНИЕ

The HMC641ALP4E is a general-purpose, nonreflective, singlepole, four-throw (SP4T) switch manufactured using a gallium arsenide (GaAs) process. This switch offers high isolation, low insertion loss, and on-chip termination of the isolated ports.

The HMC641ALP4E includes an on-chip, binary 2 to 4 line decoder that provides logic control from two logic input lines. The HMC641ALP4E comes in a 4 mm × 4 mm, 24-lead LFCSP package and operates from 0.1 GHz to 20 GHz.

ОСОБЕННОСТИ

Broadband frequency range: 0.1 GHz to 20 GHz

Nonreflective 50 Ω design

Low insertion loss: 3.0 dB at 20 GHz

High isolation: 40 dB at 20 GHz

High input linearity at 250 MHz to 20 GHz

P1dB: 24 dBm typical

IP3: 41 dBm typical

High power handling

26.5 dBm through path

23 dBm terminated path

Integrated 2 to 4 line decoder

24-lead, 4 mm × 4 mm LFCSP package

ESD rating: 250 V (Class 1A)

 

ПРИЛОЖЕНИЯ

Test instrumentation

Microwave radios and very small aperture terminals (VSATs)

Military radios, radars, and electronic counter measures (ECMs)

Broadband telecommunications systems

 

ТЕОРИЯ ЭКСПЛУАТАЦИИ

The HMC641ALP4E requires a negative supply voltage at the VSS pin and two logic control inputs at the CTRLA and CTRLB pins to control the state of the RF paths.

Depending on the logic level applied to the CTRLA pin and the CTRLB pin, one RF path is in the insertion loss state while the other three paths are in an isolation state (see Table 4). The insertion loss path conducts the RF signal between the RF throw pin and RF common pin while the isolation paths provide high loss between RF throw pins terminated to internal 50 Ω resistors and the insertion loss path.

The ideal power-up sequence is as follows:

  1. Ground to the die bottom.
  2. Power up VSS.

3.Power up the digital control inputs. The relative order of the logic control inputs is not important. However, powering the digital control inputs before the VSS supply can inadvertently become forward-biased and damage the internal ESD protection structures.

4.Apply an RF input signal. The design is bidirectional; the RF input signal can be applied to the RFC pin while the RF throw pins are the outputs, or the RF input signal can be applied to the RF throw pins while the RFC pin is the output. All of the RF pins are dc-coupled to 0 V, and no dc blocking is required at the RF pins when the RF line potential is equal to 0 V.

The power-down sequence is the reverse of the power-up

sequence.

 

APPLICATION INFORMATION

EVALUATION BOARD

The EV1HMC641ALP4 is a 4-layer evaluation board. Each copper layer is 0.5 oz (0.7 mil) and separated by dielectric materials. Figure 14 shows the stack up for this evaluation board.

All RF and dc traces are routed on the top copper layer whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. Top dielectric material is a 10 mil Rogers RO4350. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is approximately 62 mil, allowing the subminiature version A (SMA) launchers to be connected at the board edges.

The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with trace width of 16 mil and ground clearance of 13 mil for a characteristic impedance of 50 Ω. For optimal RF and thermal grounding, arrange as many plated through vias as possible around transmission lines and under the exposed pad of the package.

Figure 15 shows the layout of the EV1HMC641ALP4 evaluation board with component placement. Power supply port is connected to the VSS test point, J8, and control voltages, CTRLA and CTRLB, are connected to the A and B test points, J6 and J7, and the ground reference is connected to the GND test point, J9. On the supply trace, VSS, use a 1000 pF bypass capacitor to filter high frequency noise.

The RF input and output ports (RFC, RF1, RF2, RF3, and RF4) are connected through 50 Ω transmission lines to the SMA launchers, J1 to J5. These SMA launchers are soldered onto the board. A through calibration line connects the unpopulated J10 and J11 launchers; this transmission line estimates the loss of the PCB over the environmental conditions being evaluated.